1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to a method of producing a MOSFET with reduced overlap between the gate electrode and an LDD region.
2. Description of Related Art
The metal-oxide semiconductor field-effect transistor (MOSFET) uses a gate electrode to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the substrate being doped oppositely to the source and drain. The gate electrode is separated from the semiconductor substrate by a thin insulating layer, referred to as the gate oxide. The operation of the MOSFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical MOS processing, the source and drain are formed by introducing dopants into the semiconductor substrate. Introducing dopants by ion implantation tends to damage the semiconductor substrate. Most of the damage created by ion implantation can be annealed out at a high temperature (usually above 800.degree. C.), which drives the source and drain farther into the semiconductor substrate. Aluminum has been used as the gate electrode. However, since aluminum must be deposited following completion of all high-temperature process steps (including drive-in of the source and drain regions), the gate electrode must be separately aligned to the source and drain. The alignment procedure adversely affects both packaging density and parasitic overlap capacitances between the gate electrode and the source/drain regions.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in MOS technology. One of the key innovations is the use of heavily-doped polysilicon as the gate electrode in place of aluminum. Since polysilicon has the same high melting point as a silicon substrate, it can be deposited prior to source and drain formation. Furthermore, the gate electrode itself can serve as a mask during formation of the source and drain regions (by either diffusion or ion implantation). The gate becomes nearly perfectly aligned over the channel, with the overlap of the source and drain being due in-part to lateral diffusion of the dopant atoms.
As MOSFET dimensions are reduced and the supply voltage remains constant (e.g., 5 V), the electric field in the gate oxide tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. That is, the high electric field causes electrons in the channel to gain kinetic energy and become "hot". Such hot electrons can lose energy via impact ionization which generates electron-hole pairs that can lead to a form of avalanche breakdown. Hot electrons can also overcome the potential energy barrier between the silicon substrate and the gate oxide thereby causing hot carriers to become injected into the gate oxide. The trapped charge accumulates over time and can lead to permanent changes in the threshold voltage of the device. Changes to the threshold voltage can change other MOSFET characteristics, such as saturation current and transconductance.
MOSFET performance degradation from hot electron effects can be reduced by a number of techniques. One such technique is a lightly-doped drain (LDD). The purpose of LDDs is to absorb some of the potential into the drain and thus reduce the maximum electric field. The source and drain are formed by two implants. One of these is self-aligned to the gate electrode, and the other is self-aligned to the gate electrode on which two sidewall spacers have been formed. The sidewall spacers are typically oxides. The purpose of the lighter first dose is to form a lightly-doped section of the drain at the edge near the channel. The maximum electric field value is reduced since the voltage drop is shared by the drain and the channel (as opposed to almost the entire voltage drop across the lightly-doped channel region). Reducing the electric field on the order of 30-40% can reduce hot-electron-induced currents by several orders of magnitude. The second heavier dose forms a low resistivity region of the drain region, which is merged with the lightly-doped region. Since the heavily-doped region is farther away from the channel than a conventional drain structure, the depth of the heavily-doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bidirectional current is used), however LDD structures are typically formed for both the source and drain to avoid the need for an additional masking step. The use of LDDs has other advantages, including reducing short-channel effects such as threshold voltage rolloff.
A drawback with conventional LDD fabrication using ion implantation is that after the lightly-doped region is formed, driving-in the source and drain regions by high-temperature processing causes the lightly-doped regions to laterally diffuse beneath the gate, thereby increasing the overlap between the gate electrode and the LDD. During device operation, this overlap tends to increase capacitance which reduces switching speeds. One approach for minimizing the overlap is to exercise stringent process controls in order to reduce excessive LDD diffusions. A problem with this approach is that a certain amount of LDD diffusion and corresponding overlap is inevitable. Needless to say, a better method is needed for reducing overlap between LDD regions and the gate electrode.